Field of the Invention
The invention relates to an interpolation filter circuit for a digital communication device, in particular a DSL transceiver.
A DSL transceiver is a transmitting/receiving device for a digital communication network for the transmission of data and voice. In the DSL method (DSL: Digital Subscriber Line), the analog twisted two-wire lines in the exchange area of analog networks are used. In this case, the twisted two-wire lines form an analog transmission link for data transmission.
FIG. 1 shows the basic construction of a communication device which transmits digital signals via an analog transmission link to a further communication device (not shown). In this case, the communication device includes a data source for generating the digital data to be transmitted, which are emitted with a symbol-clock data rate or a data-symbol frequency fsymb to a circuit for filtering and clock-rate conversion. Subsequently, the filtered data are converted by a digital-to-analog converter (referred to herein as a “digital/analog converter” for simplicity) for emission to the analog transmission link. The data emitted to the analog transmission link must conform to a desired characteristic for the power spectral density, which is fixed by the transmission standard.
FIG. 2 shows the desired characteristic of the power spectral density (PSD), as prescribed for example in the case of the DSL transmission method. The desired power density characteristic essentially comprises two ranges, namely a passband frequency range, in which the power spectral density PSD is constant, and a cutoff frequency range, in which the power spectral density falls with a specific edge steepness. The 3-decibel cutoff frequency is generally half the symbol-clock frequency fsymb/2.
The digital data signal emitted by the data source is filtered by the circuit for filtering and clock-rate conversion, as it is represented in FIG. 1, in the case of the conventional communication device in such a way that the characteristic of the analog output signal emitted at the digital/analog converter coincides as much as possible with the desired characteristic of the power spectral density PSD. Furthermore, an over sampling of the digital signal emitted by the data source to the high sampling frequency of the digital/analog converter takes place. The digital/analog converter may be, for example, what is known as a delta-sigma digital/analog converter. The oversampling rate (OSR) can in this case be programmed in.
FIG. 3 shows the circuit for filtering and clock-rate conversion represented in FIG. 1 in the case of the conventional communication device.
The digital input signal emitted by the data source is initially fed to a resampling filter. The resampling filter is either a holding element or a repeater circuit, or what is known as a zero-stuffing circuit. The resampling filter connected to the input has the effect of adapting the symbol-clock data rate. Connected downstream of the first resampling filter is an FIR filter (FIR: Finite Impulse Response). FIR filters are non-recursive filters or tranversal filters and their impulse response has a finite length. The FIR filter serves for impulse shaping and sets the power spectral density PSD of the analog signal emitted by the digital/analog converter in a way corresponding to the desired power density characteristic represented in FIG. 2. Connected in series downstream of the FIR filter is a further resampling filter. The second resampling filter carries out a resampling to the sampling frequency of the downstream digital/analog converter. The high sampling frequency of the downstream digital/analog converter ensures low converter noise and adequate echo signal suppression.
The second resampling filter is connected to a comb filter for further pulse shaping. The comb pulse-shaping filter sets the edge steepness in the cutoff frequency range of the power spectral density characteristic and serves for band limitation, with image frequency bands being suppressed. The filtered digital output signal emitted by the resampling filter is emitted at the output A to the digital/analog converter for conversion into the analog output signal.
The prior-art circuit for filtering and clock-rate conversion represented in FIG. 3, which is used in the case of the conventional communication device as it is represented in FIG. 1, has the disadvantage that the FIR impulse-shaping filter receives as the input signal a digital data signal with a comparatively high data rate.Fdat=W×fsymbwhere W is typically four.
The FIR filter must therefore carry out the filtering at a high clock frequency, in order to ensure the desired power density characteristic of the analog output signal represented in FIG. 2. On account of the high data input frequency, the transmission function of the FIR filter must comprise a comparatively high number of filter coefficients F, in order that the desired power density characteristic PSD in FIG. 2 can be achieved. The high number of filter coefficients F corresponds to a high number of multipliers, adders and delay elements from which the FIR filter is constructed. With the increasing number of filter coefficients of the FIR filter, the circuitry-related expenditure increases. This ultimately leads to a higher chip area consumption of the FIR filter and consequently to higher production costs. In addition, the power consumption of the FIR filter likewise increases with the increasing number of filter coefficients of the FIR filter.